Design Engineering Architect

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. JOb Profile This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems. We are looking for a Sr Principal SI/PI Engineer who will be a key contributor to our advanced high speed IP products. This is a hands-on technical position. Main Job Tasks and Responsibilities: • Work on test chip package design SI/PI optimization and verification. • Work on evaluation board design optimization for best SI/PI performance. • Provide extracted and measured channel models for chip designers in the R&D team. • Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries. • Review customer package and board designs and simulation results. Help with providing feedback to customers to ensure best possible performance of our IP in their ASIC. • Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models. • Help with SI/PI related debug of test chips or customer ASICs in the lab. Position Requirements: • M.S. or Ph.D. Electrical Engineering (or similar degree) • 15+ years of experience preferably working with high speed SerDes and PHYs • Good understanding of high speed SerDes architecture • Hands on lab experience with instruments like high speed oscilloscopes, TDRs, VNAs, spectrum analyzers, etc. • Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave • Experience with IBIS-AMI model simulations • Experience with simulation result to lab measurement correlation • Good understanding of PCB and FCBGA design rules and requirements • Strong debugging and problem-solving skills • Excellent communication and presentation skills to effectively communicate with both customers and internal stake holders We’re doing work that matters. Help us solve what others can’t.